资源列表
spi_test
- 基于FPGA的SPI通讯测试，可以一块FPGA单独测试，也可以2片FPGA对测。-SPI communication test, based on the FPGA can be a piece of FPGA test alone, can also be 2 piece of FPGA for measurement.
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
RQDQ-4
- 4人抢答器，计时器和抢答器综合，开始抢答时，计时器从20s开始倒计时，如果无人抢答，计时器到0时报警器响3s，有人抢答，数码管会显示第几人抢答。-4 hours of answering device, timer and answer device synthesis, began to answer, the timer 20s countdown, if no one answer, the timer to 0 when the alarm ring 3s, some people a
8051
- fpga移植51单片机内核,完全兼容51单片机的开发环境-Fpga u79FB u690D1 u5355 u7247 u673A u5185 u6838, u5B8C u5168 u517C u5BB1 u5355 u7357 u673A u7684 u5F00 u53D1 u73AF u5883
UART_Rx_Tx
- fpga串口uart，实现fpga与电脑、单片机之间的通信-The fpga uart serial port, realize the fpga and computer, the communication between the SCM (single chip micyoco)
usbf_crc5
- 适用于刚入门FPGA 的人使用，简单的FPGA程序例程-Applies to people who are just touching FPGAs
Vga
- FPGA:VGA外设，实现VGA显示，VGA将会显示四种颜色，红、黄、蓝、绿-VGA peripherals, to achieve VGA display, VGA will display four colors, red, yellow, blue, green
Ad
- AD外设实验，将模拟信号输入给AD外设，AD外设将会转换成数字信号送给数码管显示对应的电压值-AD peripheral experiment, the analog signal input to the AD peripherals, AD peripherals will be converted into digital signals to digital tube display corresponding voltage value
Da
- DA外设实验，将数字信号输入给DA外设，DA外设将会转换成模拟信号进行输出1KHz的正弦波。需要使用示波器进行测量-DA peripheral experiment, the digital signal input to the DA peripherals, DA peripherals will be converted to analog signals, output 1KHz sine wave. Measurements need to be carried out using a
100Examples
- VHDP入门级教程，实用编程100例，非常适合新手，工程齐全，上手快，是Verilog语言开发工作者的必备代码。-VHDP entry-level tutorial, practical programming 100 cases, very suitable for novice, complete engineering, quick start, Verilog language development workers are essential code.
db
- 基于FPGA 的正弦波三角波方波锯齿波，的电路图及VHDL的代码-FPGA based sine wave, triangle wave, square wave sawtooth wave, the circuit diagram and VHDL code, based on the FPGA sine wave, triangle wave, square wave, sawtooth wave, the circuit diagram and VHDL code
fdiv_test_isim_beh
- VHDL主要用于描述数字系统的结构、行为、功能和接口。除了许多具有硬件特性的句子外，VHDL语言形式、描述风格和语法与一般计算机高级语言非常相似。VHDL的程序结构是一个工程设计，或设计实体（可以是一个组件，一个电路模块或一个系统）被划分为外部（或可见部分，和端口）和内部（或不可视）-VHDL is used primarily to describe the structure, behavior, function, and interface of digital systems. In