资源列表
S02_CH05_UBOOT
- 利于ｖｉｖａｄｏ的ｓｄｋ环境实现ｕｂｏｏｔ的编译-Conducive to vivado sdk environment uboot compiler
lift
- 电梯控制- U7535 u68AF u63A7 u5236 .......................................... ......................
shft
- 含同步并行预置功能的8位移位寄存器。工作原理 当CLK的上升沿到来时进程被启动，如果这时预置使能LOAD为高电平，则将输入端口的8位二进制数并行置入移位寄存器中，作为串行右移输出的初始值；如果LOAD为低电平，则执行语句： reg8（6 downto 0）< reg8(7 downto 1)-8 bit shift register with synchronous parallel preset function. The principle of work when the ri
qpsk
- QPSK数字的Verilog调制器的设计和实现-Design and Implementation of Verilog Modulator for QPSK Digital
baseed-on-EDA-of-three-BCD-counter
- 基于EDA的三位BCD计数器，实现从0到999的计数功能-based on EDA of three BCD counter
2014011494
- FPGA嵌入式开发全加法器程序。二进制运算器及数码管扫描电路-FPGA embedded development full adder program. Binary calculator and digital tube scanning circuit
FPGA
- FPGA说明书，包括接口说明以及各模块说明-Introduction of FPGA
VHDL-ELEVATOR-CONTORLLER-DESIGN
- VHDL电梯控制器程序设计与仿真，内含原理图和VHDL源码，有助于学习VHFL-VHDL u7535 u68AF u63A7 u5236 u5668 u7A0B u5E8F u8BBE u8BA1 u4E0E u4EFF u771F
weisuiji
- 伪随机m序列的代码，需要的自取，aiyo dajiasuibianle couershigezi- U4F2A u968F u673Am u5E8F u5217 u7684 u4EE3 u7801 uFF0C u9700 u8981 u7684 u81EA u53D6 uFF0C
Cam_Cap
- 基于Lattice ＦＰＧＡ的视频图像采集与ＶＧＡ输出-Video Image Acquisition and VGA Output Based on Lattice FPGA
clock
- 一个简易的数字钟，可以根据输入的时钟频率来计时-A simple digital clock can be clocked based on the input clock frequency
jsq
- 一个在ise平台上写的计算机小程序，可以计算加减乘除，输入位数为10位，三位小数-A computer on the ise platform to write a small program, you can calculate the addition and subtraction multiplication and division, the input bit is 10, three decimal