资源列表
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
OpenCores-Amber
- *硬件在OpenCore Amber ARM Core中实现-Trojan Hardware implemented in the OpenCores Amber ARM Core
OpenBTS-USRP1
- 用于OpenBTS USRP1 Cyclone FPGA比特流的Altera Quartus项目-Altera Quartus Project for OpenBTS USRP1 Cyclone FPGA bitstream
BASYS-3-Artix-7
- 使用BASYS 3 Artix-7 FPGA设计数字系统和数字逻辑的VHDL代码-VHDL code for designing digital systems and digital logic using the BASYS 3 Artix-7 FPGA
Tlc5615_Dac
- 基于VerilogHDL的TLC5615控制模块的设计-Design of TLC5615 Based on FPGA
com_exec
- 基于VerilogHDL的串口控制模块的设计-Design of Serial Port Control Module Based on VerilogHDL
traffic
- 基于VerilogHDL的交通灯仿真的设计-Design of Traffic Light Simulation Based on VerilogHDL
music
- 基于VerilogHDL的音乐播放的设计-Design of Music Playing Based on VerilogHDL
n_Bit_Counter
- n bit counter verilog code
MyClock
- 使用Verilog语言写的简单的计时器,修改引脚即可使用。-Verilog Clock
S02_CH03_EMIO
- 基于ｖｉｖａｄｏ的ＥＭＩＯ流水灯的实现，可以直接运行-Based on vivado EMIO water lamp implementation, you can run directly
S02_CH02_MIO
- 基于ｖｉｖａｄｏ的ＭＩＯ点灯的实现，可以直接运行-Based on vivado MIO lighting implementation, you can run directly