资源列表
ps2verilog
- PS2键盘解码源程序，亲测可用，希望对大家有帮助-PS2 keyboard decoding source, pro-test available, we hope to help
arm4u_latest.tar
- DESIGN OF A DYNAMICALLY RECONFIGURABLE PIPELINED RISC PROCESSOR
simple
- FIRST WORD FALL THROUGH FIFO
_MATLAB_AND_FPGA_AlteraVerilog
- 数字通信同步技术的MATLAB与FPGA实现 Altera/Verilog版- U6570 u5B57 u901A u4FE1 u540C u6B65 u6280 u672F u7684MATLAB u4E0EFPGA u5B9E u73B0 Altera/Verilog u7248
DDS
- 四通道DDS信号发生器,Four channel DDS signal generator-Four channel DDS signal generator
EDA
- 熟悉QuartusⅡ的Verilog HDL文本设计流程全过程，学习计数器的设计、仿真和硬件测试。-Familiar with Quartus II Verilog HDL text design process, learning counter design, simulation and hardware testing.
shift_reg_control
- vivado project for shift register in vhdl
interpolation
- vivado project file for down scaling of image by scale factor 2
dianti
- 实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态-dianti in verilog
ram
- 基于VHDL的教学实验机ram芯片连续读写-RAM chip based on VHDL continuous read and write
pcie_sg_dma_latest.tar
- 使用vhdl硬件描述语言实现的 PCIE DMA，资料详尽，与大家共享-vhdl for dma
C430
- 芯视清C4-30开发板的自检启动代码，里面有Audio_wm,DDR,LCD,PS2,VGA，等多个端口的自检程序-Core visual C4-30 development board self start code, which has Audio_wm, DDR, LCD, PS2, VGA, and many other self inspection procedures