资源列表
Bell2
- This an example for control a Bell in VHDL languge-This is an example for control a Bell in VHDL languge
AD7612V3
- Verilog Code of AD7612
N_CSMA
- 一种CSMA原理的描述性仿真编程，实现了站点间的类CSMA通信-One kind of CSMA descr iption of the principle of simulation programming class that implements the CSMA communication between stations
64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc
- 64Bit Look Ahead Adder Verilog Code with Testbench
EDA-digital-clock
- 显示时、分、秒，有手动校时功能，计时过程具有报时功能-Display hours, minutes, seconds, manual timing function, timing processes with chime
FP_ADDER
- This a project of FP_ADDER.-This is a project of FP_ADDER.
FP_ADDER_SUBTRACTOR
- This is FP_ADDER_SUBTRACTOR.
Ex02_BCD
- 用FPGA实现BCD功能，提供源代码，并配有文字说明。适合初学者看，语言为VHDL语言。-Realizing the ability of BCD with FPGA.Use VHDL.There are also exploin in Chinese,which is suitable to the freshman.
fullAdder_4bit
- This is fullAdder_4bit with testbench.
counter-with-T_FF
- This is counter with T_FF.
decoder
- This decoder by VHDL.-This is decoder by VHDL.
VerilogExperiment_v2
- verilog那些事儿_时序篇程序,请需要的人员下载参考-verilog timing of those things _ Chapter program, please download the reference staff needed