资源列表
BCDto7Segment
- vhdl bcd to seven segment
7Segment2bcd
- vhdl seven segment to bcd 4 bit
7Segment2bcd8bit
- vhdl seve segment to bcd 8 bit
freq_meter
- FPGA的测频程序，用了D触发器，能测1hz到几百hz-FPGA frequency measurement procedures, using a D flip-flop, can be measured to a few hundred hz 1hz
jiaotongdeng
- 基于FPDA的交通灯课设，功能老师以及验证过，真实能用。各模块截图也有，方便理解-FPGA-based class-based traffic light, functional and verified teacher, real use. Each module also has a theme, easy to understand
linear
- 线性分组码编码电路和译码电路实现程序，仿真测试文件-Controls, coding, simulation test file linear block code
Lab_Code_Solution
- A Basic SoC Platform
simple-uart
- 书写的简单串口通信，可用于FPGA,与电脑连接，测试可用。-a simple uart communication，it can be used in FPGA，it can communicate PC to the FPGA by this code.
MUL
- 4位乘法器用来监测心跳到，与计数器搭配使用-this is 4 multiply to get heart beats
DW_apb_timer
- verilog实现计时器timer，可直接用于芯片开发中。-verilog achieve timer, it can be directly used for chip development.
DTCNT9999
- 9999计数器，源代码用VHDL进行书写，设计中有计数模块，动态扫描模块，动态显示模块。书写规范，易于理解。-9999 counters, source code written in VHDL are, in the design of counting module, dynamic scanning module, dynamic display module.
fm0_encode
- fm 0 encode source code by using verilog