资源列表
del_skew
- 按键消抖的verilog代码，在fpga开发板上可用，有按键功能的设计如果不消除抖动，可能会造成误触发-a cut key skew verilog code ,it can work on fpga card,key cut skew is very importent,the design may have error without the code.
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector
simple_spi_latest.tar
- 基于vhdl的spi主从模式的程序，实现简单的SPI收发，对于实际使用学习是个比较好的例子！-VHDL SPI master-slave mode based on the procedures, the realization of a simple SPI transceiver for practical use, is a good example of learning!
VHDL-Programming-Examples
- 分频器、译码器、编码器、计数器、状态机等基本的硬件描述语言代码-The basic hardware divider, decoders, encoders, counters, state machine descr iption language code
rom
- 生成rom的代码-The code generated rom.。。。。。。。。。。。
Stepper-motor
- 步进电机驱动模块设计，使用硬件描述语言设计。-Stepper motor driver module design, using a hardware descr iption language design.
Stepper-motor-speed
- 步进电机控制模块主要包括步进电机调速控制，该模块实现步进电机可由外置拨码开关来控制电机转速。-Stepper motor control module comprises a stepper motor speed control, the stepper motor module by external DIP switches to control the motor spe
BERT.ZIP
- BER test for asynchronous interface, e.g.RS485, RS232. selectable 2^11 or 2^15.
Descending-ramp
- 递减斜波是一种原理和递增斜波相似的波形，只需将递增斜波的循环加法计数换成1111 1111 1111～0000 0000 0000循环减法计数即可。-Harmonic is a descending ramp and incremental principle similar waveforms, simply incremented counts up the ramp into the cycle of ~ 1111 1111 1111 0000 0000 0000 cycle counti
VHDL_paobiao
- 用VHDL语言设计一个跑表，计时范围为59.99秒。-Write a time range using VHDL language to 59.99 seconds in the stopwatch
DE2_Basic_Computer
- DE2 altera board vhdl design
vhdl416yima.doc
- 四十六译码器 是用if语句描述的-library IEEE use IEEE.std_logic_1164.all entity encoder4_16 is port ( d: in STD_LOGIC_VECTOR (3downto0) q: out STD_LOGIC_VECTOR (15downto0)) end encoder4_16 architecture encoder_if of encoder4_16 is begin