资源列表
QAM
- QAM基带调试，星座映射方法，带有m序列作为信源-QAM baseband debugging, constellation mapping method
m
- 为随机序列产生器，可以作为调制信号的信源-As the random sequence generator, can be used as a modulation signal source
IQ_sin_cos
- Cordic根据输入的IQ正交两路信号求取对应的正余弦值-Cordic according to input the IQ of orthogonal cosine signal to calculate the corresponding two road is
IQ_sin_cos_mod
- Cordic根据输入的IQ正交两路信号求取对应的正切值-Cordic according to input the IQ of orthogonal signal to calculate the corresponding tangent value two road
my_i2c
- 基于FPGA的i2c通信，使用Verilog hdl实现，带有功能说明文档、ise工程、modelsim仿真工程-i2c communication based FPGA using Verilog hdl implementation, with the function documentation, ise project, modelsim simulation project
gaussian
- This Gaussian lvbo program please downing this matlab blur ok yes -This Gaussian lvbo program please downing this matlab blur ok yes
SDRAM_96M
- 基于FPGA的SDRAM串口实验，verilog语言写的，附件里是做实验的工程，连上串口，下进去就有数据了，波特率9600，一个停止位，SDRAM时钟是96MHz，数据时FPGA自动产生的，正确输出结果是00到FF递增一，再循环。这个工程警告比较少，基本是故意为之的警告，时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even o
UART-botelv115200
- 基于FPGA的串口收发程序，波特率115200，亲测，可用。-FPGA-based serial transceiver procedures, 115200 baud rate, pro-test, can be used.
MUX41
- 四选一的选择器 FPGA源码，包括模块Verilog文件和测试testbench文件-Four one of the selector FPGA source code, including the module Verilog files and test testbench files
ADDR
- 8位全加器，包括半加器verilog文件，全加器verilog文件，8位全加器verilog文件，和8位全加器测试testbench文件-8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file
cnt2
- 16位二进制计数器及设计代码其测试代码（vhdl）-16-bit binary counter and design codes and test code (vhdl)
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction