资源列表
conv_encoder(rate=1_2)
- 这是用ISE编写的verilog语言1/2码率的卷积编码的代码-It is written in verilog language ISE convolution coding rate 1/2 code
anish-bit-masking
- vhdl code for bit masking algorithm
05413cordic
- VHDL CODE FOR CORDIC ALGORITHM
pll_prj
- PLL配置仿真实验 PLL，即锁相环。简单的理解，给PLL 一个时钟输入（一般是外部晶振时钟）， 然后经过PLL 内部的处理以后，在PLL 的输出端口就可以得到一定范围的时钟频 率。其之所以应用广泛，因为从PLL 输出得到的时钟不仅仅从频率和相位上比较 稳定，而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
AX301_led_test_code
- 黑金AX301开发板led相关实验程序代码-AX301 development board LED test code
AX301_Real_time_clock_test
- AX301 FPGA开发板，实时时钟实验程序代码-AX301 FPGA development board,Real time clock test code
sdram_learn_8bit
- fpga 学习资料，老师给的，讲如何实用ram,比较实用-learning information for beginning learners
a_vhd_16550_uart
- Using the UART core is the similar to using the standard 16550 UART, expect that the FIFO’s are always enabled, and there is no sticky parity.
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
Divide
- This a divider verilog code
ALU
- This MIPS ALU verilog code-This is MIPS ALU verilog code
Mux4
- This Mux4 verilog code.-This is Mux4 verilog code.