资源列表
sha1
- SHA1 hashing algorithm core.Basic architecture modified to perform 5 basic algorithm steps at single clock cycle.
pd
- 使用线性CCD测量2点之间的距离。FPGA的源代码-CCD FPGA
COM_REV
- 基于FPGA的串口接收程序,标准通用的串口接收程序-FPGA-based receiver program
DDR-SDRAM-Controller
- DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
Verilog_study
- 常用逻辑器件硬件描述合集,Verilog描述已通过编译，可直接嵌入使用-Hardware descr iption collection of common logic devices
ethernet_test
- 以太网FPGA通信,verilog代码，实现双向通信-Ethernet FPGA communication
QD
- 四路抢答器，主持人复位之前抢答算做犯规，复位之后抢答第一个人有效，其余无效。并且均有组别显示与声音示警。-Four Responder, Responder counted reset before the host foul, the first person to answer in an effective after a reset, the rest is invalid. And have a group show with the sound warning.
qdjs
- 10s倒计时，在复位高电平期间，开始倒计时，有某信号(抢答信号)输入，则恢复到10s并保持，准备下次计时。-10s countdown, at a high level during reset and start the countdown, there is a signal (answer signal) input, then back to the 10s and remains ready for the next timing.
ug612
- xilinx的时钟约束指导，适合新手学习-xilinx clock constraint guidance documents for novices to learn
FULL_ADD
- 编写一位全加器的程序，生成器件后用BLOCK画出bdf图，最终成为四位全加器。此为实验报告，里面包括原理及框图及源程序。-Preparation of a full adder program, after generating device using BLOCK draw bdf map, eventually become four full adders. This is a test report, which includes the principle and block diag
xilinx_license_2015
- Vivado Design Suite v2015.4版本license-the license of Vivado Design Suite v2015.4
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench