资源列表
alt_xaui
- altera ip a ltera ip-altera ip altera ip altera ip
DTSM
- 在开发板上可以实现从00到59的计数，相当于一个60进制的计数器，里面包括了将脉冲分频的代码编写-In the development board can be achieved 00 to 59 counts, the equivalent of a 60 hexadecimal counter, which includes the pulse frequency of the code
descore_latest.tar
- VHDL implementation of the classic DES block cipher (interactive architecture)
pwm_latest.tar
- pulse width modulator, work as one PWM or one timer. 16 bit main counter
scalable_arbiter_latest.tar
- a scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speed with up to hundreds of request lines, and it grants in just a few clock cycles.
statled_latest.tar
- a simple module to get the most of your on board heartbeat LED change or add more sequences easily in parameters file
vhd2vl-2.4.tar
- convert VHDL files to Verilog files
VGA_Qin
- VGA实验中，根据要求，动态显示图片，图片的动态效果是触及屏幕反弹 -VGA experiment, according to the requirements, dynamic display picture, dynamic picture of the effect of the screen is touched rebound
Xilinx_example
- xilinx 多核嵌入式系统设计的配套光盘源代码-Xilinx multi-core embedded system design form a complete set of CD source code
LTC2440_1
- 一款具有 5ppm INL 和 5μV 偏移的高速 24 位无延迟增量累加 (No Latency ΔΣTM) ADC LTC2440的源代码-A 5ppm INL and 5 V high speed 24 bit offset without delay increment accumulation (No Latency TM ADC LTC2440 delta sigma) source code
DDR_TEST_OK
- 接口DDR2读写测试模块，好用，测试正确-Interface DDR2 read and write test module， ，test correctly
FSK_MODULATION_DEMODULATION_CODE
- FSK调制与解调VHDL程序_好用_测试正确-FSK modulation and demodulation of VHDL program _ with _ test correctly