资源列表
vga_interface
- 使用verliog实现vga接口的封装，使用altera cyclone第四代验证通过-Use verliog achieve vga interface package, use altera cyclone verified by the fourth generation
booth_multiplier
- 使用verliog设计实现booth乘法器，通过modelsim仿真验证通过-Use verliog design implementation booth multiplier by simulation by modelsim
booth_multiplier_modify
- 使用verliog改进传统的booth乘法器，通过modelsim仿真验证通过-Use verliog improve the traditional booth multiplier, verified by simulation by modelsim
lut_multiplier
- 使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过-Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim
1_2
- 基于cyclone EP1C6Q240C8的流水灯设计样本-a sample design of light water based on cyclone EP1C6Q240C8
sevenSegmentModule
- VHDL code for four digit seven segment displays. Blinking feature is included
LED_ctrl
- altera C3系列FPGA的一个简单的LED例程，引脚已分配，可以直接使用~-C3 Altera series FPGA of a simple LED routines, pins have been allocated, can be directly used ~
uart_mod
- 与上位机通信的串口驱动程序，基于VHDL语言-uart module
demodul_2ASK_NonCoherent
- 2ASK 非 相 干 解 调, verilog编程实现-2ASK non-coherent demodulation, verilog realization
1-flowingled
- 基于Xilinx Spartan6 简单的流水灯实验 VHDL -Based on Xilinx Spartan6 simple VHDL test water lights
mu0
- 基于Xilinx Spartan6的 一个简单的CPU MU0 VHDL-Based on a simple CPU Xilinx Spartan6 of MU0 VHDL
11-songer
- 基于Xilinx Spartan6的FPGA案例 播放 梁祝 的程序 VHDL-Play Lovers of FPGA-based Xilinx Spartan6 case program VHDL