资源列表
first_zynq_design
- zedboard开发板的一个程序 搭了一个简单的硬件平台 然后软件是实现led灯的控制-zedboard vhdl code to control led on the board
FIR.ip
- zedboard 开发板学习资料 FIR滤波器的 代码 -code to implement the FIR function on zedboard
SoCKit_Audio
- SoCKit_Audio，使用SoCKit FPGA开发板，使用SSM2603视频编码ADC芯片，进行视频传输处理，使用verilog语言。
High-level-synthesis
- 电子系统设计高层次综合high level synthesis 讲解文档,包括基本概念和流程,工具,方法等-powrpoint format document about high-level synthesis ,including concetpions,flows ,examples
High-Level-Design-with-SystemC
- 电子系统设计使用system C进行高层次综合high level synthesis 讲解文档,包括基本概念和流程,方法等-high-level synthesis with system C language,this document intoduce concetps,methods and flow
sch
- 电子系统设计高层次综合high level synthesis 源码,C++ 实现调度-electronic system level HLS design, cpp code for scheduling
Catapult_HLS-by-C
- 电子系统设计高层次综合high level synthesis工具 Catapult使用及利用C++进行算法开发讲解文档-document about Catapult (HLS tool)using c++ for designing
Exercising-H.264-Video-Compression-IP-Using-Comme
- This book describe about Exercising-H.264-Video-Compression-IP-Using-Commer.
MTM_UEC1_lab04_raportfinalny
- verilog hdl BCD to 7seg converter with testing module
uart_mm
- Its uart transmitter and receiver
SDRAM controller
- This SDRAM controller is useful for SDR_SDRAM IC's can be integrated with the verilog code. The code is developed for the altera FPGA's and it can be ported to other FPGA's easily. The code is verified with terasic DE2-115 board and DE2 boards.
Piano_vhdl
- Here is the Piano code for FPGA(Basys 2) with switches.