资源列表
135-classic-Verilog-design-example
- Verilog的135个经典设计实例，移位寄存器，串并转换，交通灯控制等-135 classic Verilog design example, the shift register, string and conversion, traffic light control, etc.
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
clockdiv
- Clock division implementation on verilog VHDL
Sunhaibo
- ＰＣＩ9054的读写，其中包括双口ＲＡＭ，以及寄存器的使用-PCI9054 read and write, which includes dual port RAM, as well as the use of registers
M_UartRecv0
- rs232串口基于VHDL的代码 很有用的 正确的 rs232串口基于VHDL的代码 很有用的 正确的-RS232 serial port based on VHDL code is very useful for the correct RS232 serial port based on VHDL code is very useful
M_UartRecv0_tb
- rs232串口基于VHDL的testbench代码 很有用的 经过验正的 -RS232 serial port based on testbench s VHDL code is very useful to the RS232 serial port based on testbench VHDL code is very useful to pass the test
UART VHDL
- UART RS232 VHDK DEVELOPMENT
UART-PC
- The followed code is the design of one comunication Type UART asychronous
1802-bell-liangzhu
- 基于FPGA的音乐播放器，采用VHDL语言-FPGA-based music player, using VHDL language
temp
- 基于FPGA的一个温度传感系统 用verilog语言编写 基于basys2开发板-FPGA verilog basys2
AD
- 基于FPGA的AD采集系统 用verilog编写 基于basys2开发板-FPGA AD verilog basys2
DA
- DA转换 基于FPGA 用verilog编写 基于basys2开发板-DA FPGA VERILOG BASYS2