资源列表
RISC_CPU
- 毕业设计，基于Xilinx Spartan6自制开发板实验。毕业设计，能够实现简单的计算器。VHDDL-Graduation design, development board based on Xilinx Spartan6 homemade experiment. Graduation design, to achieve a simple calculator. VHDDL
8-TFT_24
- 基于Xilinx Spartan6自制开发板实验，2.4存TFT屏静态刷新特定图片。如果要修改图片，请使用Matlab将图片生成*.coe格式，生成ROM加载。-Development board based on Xilinx Spartan6 homemade experiment, 2.4 TFT screen kept static refresh specific picture. If you want to modify the picture, the image is gene
fifo
- 异步FIFO的实现，很经典的三段式状态机的写法。-The realization of the asynchronous FIFO, very classic three-step writing state machine.
clock
- 用verilog实现数字时钟，测试过基本上满足要求，适合初学者学习-Use verilog digital clock
spi
- 用verilog实现spi接口的简单小程序，适合初学者学习。-Use verilog implementation of spi interface simple small program, suitable for beginners to learn.
compare
- 用verilog实现文件输入的比较器，如果同一时间输入的数据相同则输出高电平，否则输出低电平，达到比对的效果。-Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.
changewin
- 用verilog实现40比特的串并转换，激励文件同时写在程序中。-Use verilog implementation 40 bits of string and transform, incentive documents written in a program at the same time.
ELECTRONICCLOCK
- VHDL语言设计的电子钟，并且有暂停功能和清零功能的按键实现，并且带秒表-VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
sixty_test1
- 模六十计数器，在basys2实验板上选择右边两个数码管计数，从0到59.依次加一。-count sixty
cpu3
- 简易CPU可执行8条简单指令,如：add,xor,and等-risc cpu
Source_Code
- Xilinx的IP核源码例化，可实现分频和倍频处理，亲测成功-Xilinx instantiated IP core source code, which can realize frequency and frequency doubling processing, measuring success
18_uart
- FPGA的串口程序,有串口控制器，串口发送，串口接收模块和顶层测试 模块等。-verilog code about the FPGA uart module.