资源列表
udp_ip_stack_latest.tar
- Udp-IP Stack for ethernet on fpga (vhdl descr iption)
Dual_ram_verilog_CODE
- 写了FIFO中要用到的双口RAM的模块,FIFO中的RAM只用于读数据,输出数据,用写时针采集信号,读时针那一端不用读时针来采样.-Written to use the FIFO dual port RAM module, FIFO in the RAM is only used to read data, output data, the clock signal acquisition with write and read without reading that end of the h
FPGA_CLK
- FPGA时钟分频的源代码，已经测试通过！-FPGA clock divider source code, has been tested!
FPGA_UART
- 在Verilog环境下，实现多个串口的功能，支持波特率，数据位，停止位可设。-In Verilog environment, to achieve multiple serial ports, support for baud rate, data bits, stop bits can be set.
shuzizhong
- 我做的是基于fpga的一个数字钟的设计用的是xilinx ise开发环境-What I do is design a digital clock based fpga xilinx ise with the development environment
MID_FILTER
- 中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。-Median filtering algorithm verilog realization available FPGA-based embedded image processing system.
PHY_MDIO
- 光纤模块实现点对点通信，千兆网传输，基于FPGA，采用Verilog语言进行编程，实现千兆网模块的高速传输-Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module
ALINX9226_406
- 采用了两片 ADI 公司的 AD9226， 此芯片是一款单芯片、 12 位、 65 MSPS 模数转换器（ ADC），采用单电源供电，它数据速率达 65 MSPS。该资料基于fpga采用verilog语言实现编程。-Using two ADI' s AD9226, this chip is a single chip, 12, 65 MSPS ADC (ADC), a single power supply, which speeds up data 65 MSPS. The data b
BCD_7SegFPGA
- Implement a generic converter BCD to Display 7 segment in a FPGA
ConterFPGA
- Implementing a Generic Conter in VHDL - FPGA
chuanbing
- FPGA里关于串并转化的一些思路和相关的代码，供大家分享。-Some thoughts on the FPGA serial conversion and related code, for everyone to share.
Ex_1
- A VHDL ABOUT ANALOG TO DIGITAL CONVERT.