资源列表
vga
- vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a
add
- The circuit 1 in is a 1-bit binary adder with 3 inputs (A, B and Carry-In) and 2 outputs (Sum and Carry-Out).The circuit 2 depends on circuit 1 which create a VHDL file ADD4 which is a 4-bit binary adder built using ADD1 components.
sayeh
- The SAYEH (Simple Architecture, Yet Enough Hardware) is a processor architecture that has been developed by Navabi in [1] for experimental and teaching purposes. As the name implies it is a “simple” architecture but contains sufficient hardware to ma
parkingfee
- 数字系统课程设计-自助停车缴费系统，该程序模拟汽车入库出库，进行计时和计费。-Digital System Design Course- Self-parking payment system, the program simulates a car storage library for timing and billing
CPU
- 完整仿真CPU功能，包括中断功能，查询功能，加减乘除和逻辑运算等。-Complete CPU emulation functions, including interrupt function, search function, arithmetic and logical operations and so on.
Lab10_Part1
- Verilog code for Altera Part1 Lab10
water
- 基于FPGA的流水灯设计，可以检验晶振是否正常工作，时钟晶振为48M-Running water light design based on FPGA makes possible the testing of crystals is working correctly, the clock crystals of 48m
led_water
- 用VERIlog语言编写的FPGA流水灯程序，已经实现，可以立即使用-VERIlog language FPGA with light water program has been implemented, you can use immediately
tuxingandvhdlsheji
- FPGA开发实例之 图形和VHDL混合输入的电路设计。 注：编译时请将文件放在英文目录下面-The FPGA development instance of graphic and VHDL mixed input circuit design. Note: please send files in directories below in English at compile time
7renbiaojueqi
- FPGA开发实例 之 用VHDL设计七人表决器-The FPGA development instance of the design with VHDL voter of seven people
duogongnengshuzizhong
- FPGA开发实例 之 多功能数字钟.多功能数字钟应该具有的功能有：显示时－分－秒、整点报时、小时和分钟可调等基本功能。-FPGA development instance of multi-function digital clock. The function of the multi-function digital clock should have are: show- points- second, hour, hour and minute basic function such a
shuzimiaobiao
- FPGA开发实例 之 数字秒表.七段码管显示.秒表由于其计时精确，分辨率高（0.01秒），在各种竞技场所得到了广泛的应用。-FPGA development instance of digital stopwatch. 7 yards tube display. Stopwatch because its timing precision, high resolution (0.01 seconds), the income to the extensive application in var