资源列表
music_player
- 音乐播放器，各模块使用VHDL写的，拥有暂停功能。jishu模块根据时钟信号产生八位递增的地址信号，传到music模块。music模块存放音乐的数据，根据得到的地址输出音阶。tonetab接收到音阶信号后会输出当前的音阶是多少，是否为高八度，用于数码管显示，同时将此音阶需要的分频率传给speaker模块。speaker模块根据接受到的分频比对2M的时钟进行分频，然后送给蜂鸣器发出声音。-Music player, each module written in VHDL, with pause f
VHDL--VGA
- 此VHDL语言程序可以控制液晶屏幕任意动画播放-The VHDL language program can control the LCD screen any animation
base-on-FPGA-cpu-
- 基于FPGA的嵌入式CPU的制作，包含了代码和测试程序，以及在UBUTNU环境下的调试工具-FPGA-based embedded CPU card, contains code and testing procedures, as well as in UBUTNU environment of debugging tools
fpuvhdl_latest.tar
- floating point unit which gives more precision output
VHDL-1-7
- VHDL课程的7个实验的实验报告附代码。-seven experiment reports of VHDL
music-by-FPGA
- 音乐发生器，使用FPGA产生音符，实测通过。-music by FPGA
lab4
- s the design and simulation of a simple traffic light controller: The controller consists of a clock divider block, two sequential circuits: a timing counter and a signal generator (state generator), and a decoder. The counter is used to define a
risc8
- 八位简易risccPU，采用verilog描述，FPGA实现-8bit risc CPU
vga
- VGA控制器，Verilog描述，ISE工作环境-VGA controler
RS_255_223_ENCODER
- rs255编码解码器，verilog描述，FPGA实现-RS255 223 ENCODER
state-machine
- 一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理-A simple realization of a vending machine with verilog state machine design, there are design principles introduced word
Synchronous-FIFO-
- 一个用verilog实现的同步fifo设计，压缩包里有word介绍设计中各信号的作用-Achieve a synchronous fifo with verilog design, compression bag has the role of word describes the design of the signals