资源列表
A_FIFO
- 自己编写的Verilog 异步fifo 有一定的个参考价值 -Verilog 异步 Fifo
S_FIFO
- 自己编写的同步Verilog FiFO 还是不错的 可以-Verilog 同步 FIFO
CIC
- 很好的级联积分梳妆CIC滤波器verilog 源代码，希望对大家有所帮助-Good cascade integral dressing CIC filter source code, hope to be of help for you
CLK_div
- 用verilog写的分频器，包括16分频，8分频，4分频，2分频等，代码简单，效率高，个人感觉很实用且对初学者很有帮助-Written in verilog divider, including 16 points frequency, frequency eight points, 4 points frequency, frequency division 2, etc., the code is simple, high efficiency, personal feeling is ve
half_band
- 半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考-Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference
cyclone_ivProgramming-Guide
- 本应用笔记提供了一组简单易用的指南和一列在Cyclone® IV 设计中需要考虑的因素。 Altera 建议在设计过程中遵循本应用笔记中介绍的指南-This application note provides a set of simple and easy to use guidelines and a list of needs to be considered in the Cyclone IV design factors. Altera is recommended t
md5
- md5算法的vhdl实现，并配有测试用例，并没有使用任何xilinx的library，用modelsim se进行仿真-md5 algorithm based on fpga in vhdl
taxifee
- 用Verilog语言完成出租车计价器的功能-Verilog language used to complete the taxi meter function
Verilog
- 关于学习vhdl的一些基本资料，老师上课的课件，对于初学者非常有用。-Vhdl learn some basic information about the teacher in the class courseware, very useful for beginners.
OV7670_config
- 本代码主要实现OV7670的初始化配置，包括主模块及参数设置、I2C传输模块！-The main achievement of the initial configuration code OV7670, including the main module and parameter settings, I2C transmission module!
clock
- 用Verilog编程设计出一个具有计时，校准，闹钟，日历等功能的电子时钟； -Design a program with Verilog have time, calibration, alarm clock, calendar and other functions of electronic clock
iic_rw
- eeprom的iic控制读写，verilog编写-eeprom iic verilog