资源列表
shuzizhong
- 基于CPLD的智能数字时钟VHDL设计，能实现时钟、秒表、闹钟、定时等功能-ntelligent digital clock CPLD VHDL-based design enables the clock, stopwatch, alarm clock, timer, and other functions
led
- 利用quartusii软件编程平台实现led点阵的汉字滚动显示功能，模拟广告牌-Quartusii use software programming platform led dot matrix character scrolling display, analog billboard
HUAWEI-Verilog
- 华为公司的Verilog HDL典型电路设计指导，仅供公司内部使用，内含全部源码，有很大的硬件设计指导意义。-Huawei s Verilog HDL typical circuit design guidance for internal company use, containing all the source code, there are a lot of hardware design guide
rom
- vhdl veri log rom file
AdcInterfaces
- A VHDL Code For ADC Interfaces
lcd
- ps2键盘，按键实现 在LCD上显示字符，字母大小写，数字，标点符号都可以显示-ps2 keyboard, the keys to achieve display characters, capitalization, numbers, punctuation marks can be displayed on the LCD
circle-of-music
- 基于FPGA的音乐播放，通过录入音乐的音符，在FPGA开发板上实现播放，verilog代码完整-FPGA-based music player, music notes by entry in the FPGA development board to achieve broadcast, verilog code integrity
fftshixian
- 基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换-FPGA-based verilog code written in xilinx FFT transform Simulation
chuanbing-and-bingchuan
- 基于FPGA的通信，实现串并并串转换，简单容易理解，代码完整，希望对你们有帮助-FPGA-based communication, and achieve string and string conversion, simple and easy to understand, code integrity, and I hope you have help
cuce(ok)
- 在起始信号与停止信号之间计数，而且通过仿真验证成功-Between the start signal and stop signal counts, and success is validated by computer simulation
ALU
- 自己编写的Verilog ALU 效果还不错 可以-Verilog ALU
ps_to_sp
- 自己琢磨的 Verilog 并行数据 转串行数据 串行数据转并行数据 有一定的个参考意义 -Verilog PS_to_SP