资源列表
AES
- AES加密和解密算法的硬件语言描述，很值得大家来学习！-AES hardware encryption and decryption algorithm descr iption language, it is worth learning!
Achievetrafficlights-
- 实现红绿灯的仿真，程序简单易懂，很适合新手和初学者-Achieve traffic light simulation, a simple program to understand, it is suitable for novices and beginners
FPGA-based-hand-gesture-recognition-system
- FPGA based hand gesture recognition system
DCT_Final
- 8 point approximate dct for image compression the purpose compression algorithm
small8
- This a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA. -This is a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA.
4bit-microprocessor
- This file is 4bit microprocessor that included a variety of modules like ALU,Progrem Counter and ACC etc It is to calculate 4bit binary Topblock is top level module.
EP2C5T144_VGA
- VGA EP2C5T altera QuartusII VHDL FPGA CPLD passed
PEX8311_test
- PEX 8311 OK PCI e cycloneIII altera quartus FPGA CPLD
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
S1_38yima_NEW
- 本次实验主要实现一个 3/8 译码器,在本实验的程序中是由 SW1、 SW2、 SW3 分别对应三位的二进制。 SW3 SW2 SW1 ： 所对应数字及二极管 0 0 0 ： 0 DD1 0 0 1 ： 1 DD2 0 1 0 ： 2 DD3 0 1 1 ： 3 DD4 1 0 0 ： 4 DD5 1 0 1 ： 5 DD6 1 1 0 ： 6 DD7 1 1 1 ： 7 DD8-This experiment mainly to achie
S2_counter_NEW
- 设计一个以十进制为基础的计数器，实现从 0 开始的计数功能；本实验主要是利用开发板上面的数码管实现一个十进制计数器的功能，计数范围0000-9999，可实现循环计数。先输入verilog 程序，然后在 QuartusII 中做波形仿真，通过后下载程序在数码管上查看计数器的功能。-Designing a decimal-based counters, a zero-counting function this experiment is the use of digital control b
S3_SW_PB_NEW
- 设计一个通过按键（ PD)和拨码开关（ SW）来控制 LED 灯的实验 本实验是利用底板上的按键及拨码开关来实现对 LED 灯的控制，其中对应关系为SW1—SW6 分别对应 DD1—DD6，PD1—PD8 分别对应 DD1—DD8。-Design is controlled by a key (PD) and a DIP switch (SW) LED lamp experiment this experiment is the use of keys and the DIP switch o