资源列表
vga789
- 这是一个Verilog的文件。可以实现在液晶显示屏山显示一副图像。-This is a Verilog file. Can display an image on the LCD Hill.
halfadder.v.tar
- Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...
fulladder.tar
- Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
basicgates
- Verilog Code for Basic Gates implementation with testbench-Verilog Code for Basic Gates implementation with testbench..
mux4_1
- Verilog Code for 4*1 Multiplexer with testbench file-Verilog Code for 4*1 Multiplexer with testbench file...
8bit_decoder
- Verilog code for 3*8 Decoder Circuit with testbench file-Verilog code for 3*8 Decoder Circuit with testbench file....
UART_RX
- 这是借鉴别人的带有FIFO的Verilog代码分享给大家，共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together
baud_gen
- Uart是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中。其中本代码为UART的波特率产生代码。-Uart is a universal serial data bus, used for asynchronous communication. The bus bidirectional communication, can realize the full duplex transmission and reception. In embedded
ise_keygen7.1-8.1-9.1
- 赛灵思的ise718191的lic-xilinxs ise718191 lic。。。。。。。
CNT10
- vhdl设计的十进制计数器，仿真测试正确，可以使用。-decimal counter vhdl design, simulation tests correctly, can be used.
adder4bit
- VHDL设计的四位加法器器，仿真测试正确，可以使用。-VHDL design of four adders, a simulation test correctly, you can use
LS194
- VHDL设计的194集成电路，仿真测试正确，可以使用。-194 IC VHDL design, simulation tests correctly, can be used.