资源列表
music
- VHDL电子琴，采用vhdl编写，通过蜂鸣器发出7种不同频率的音阶实现简易电子琴功能。-VHDL electronic organ, written by VHDL, the realization of simple electronic organ function in 7 different frequency scale through the buzzer.
PLL
- fpga锁相环的使用例程，可以教您如何使用PLL锁相环。-FPGA phase-locked loop using the routines, can teach you how to use PLL phase locked loop.
singt
- 使用FPGA产生一个正弦波，里面带有嵌入式逻辑分析仪的仿真文件。-Using FPGA to generate a sinusoidal wave, simulation files with embedded logic analyzer.
speak3
- 在FPGA上实现简易电子琴功能，再加上了一个实时时钟功能，时钟很稳定，很精准。-The realization of simple electronic organ function in the FPGA, coupled with a real time clock, the clock is very stable, very accurate.
sin
- 在Altera DE2-70的开发板上实现产生正弦波信号。-Achieve generate sine wave signal at Altera DE2-70 development board.
Rectangular-wave
- 在Altera DE2-70的开发板上实现产生矩形波信号。-In the Altera DE2-70 development board to achieve a square wave signal generated.
Sawtooth
- 在Altera DE2-70的开发板上实现产生锯齿波信号。-In the Altera DE2-70 development board realize sawtooth signal.
Crossover-design
- 在Altera DE2-70的开发板上实现分频计设计。-In the Altera DE2-70 development board to achieve crossover meter designs.
frequency-meter-design
- 在Altera DE2-70的开发板上实现频率计设计。-Achieve frequency meter design Altera DE2-70 development board.
crc_peripheral32
- 附件是32位循环冗余校验码的硬件语言（v语言）实现。-Attached is a hardware language 32 cyclic redundancy check code (v language) implementation.
Verilog-example
- Verilog 例子 说明，值得借鉴，学习Verilog的新手过来看看吧-Verilog example
cic3s200
- cic抽取滤波器,用于采样率远高于信号频率的情况下。-cic filter