资源列表
SW_HEX
- SW_HEX.rar是verilog编写的按键计数功能源代码-SW_HEX.rar is written in verilog achieve counting function keys
DE2_70_NET_UART_DMA
- 采用NIOS编写c代码实现dma传输，加入dma9000网络传输功能-Write c code using NIOS dma transfer, adding dma9000 network transmission function
ad7606
- ADC7606的驱动代码，采用verilog实现-ADC7606 driver code, using Verilog to achieve
16_clk_generator
- 简单的任意分频源码,可以通过调节参量改变输出频率-Simply divide any source, the output frequency can be changed by adjusting the parameters
LED
- QuartusII 9下的LED灯示例，很简单的例子，可以直接运行-The sample of LED of quartus II 9.0 with the language of Verilog
Simple_Logic_Continue
- quartusII 9编写的74161模块，简单的例子，可以直接运行-The module 74161 with the language of verilog
XC2C
- 基于FPGA的8路心电数据采集，发送给MSP430.-FPGA-based 8-channel ECG data acquisition, send MSP430.
fenpin
- 关于FPGA的分频程序，使用VHDL书写，可用于模块化编程-fractional frequency
shuzishizhong
- FPGA代码，数字时钟，可调小时，分钟，秒钟，调节时闪烁-digital clock
seg
- 四位一体数码管显示，实现数码管动态显示。已经测试，很好用！-Four digital tube display, realize the dynamic display of digital tube.Already test, very good!
i2s_latest
- Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL De
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum