资源列表
CRC32_D82
- CRC 校验 // polynomial: (0 1 4 5 7 8 10 11 12 16 18 22 23 26 32) // data width: 8 // convention: the first serial bit is D[7]- // polynomial: (0 1 4 5 7 8 10 11 12 16 18 22 23 26 32) // data width: 8 // convention: the first serial bit i
FPGALVDS
- FPGA差分转单端（xilinx）,操作介绍，从源码角度介绍-FPGA differential to single ended (Xilinx)
dds
- NCO，同时产生cos和sin信号。quartus -NCO, while producing cos and sin signals. quartus II
verilog--dianhuajifei
- 详细介绍了电话计费系统的计时，计费！详细的程序说明-Details of the timing telephone billing system, billing! Detailed descr iption of the procedures
vga_module
- //VGA 800*600,60Hz //red 5 green 6 blue 5 //blue4..blue0 green5..green0 red4..red0-//VGA 800*600,60Hz //red 5 green 6 blue 5 //blue4..blue0 green5..green0 red4..red0
ir_module
- ir_module with verilog code for controller remote
LCDFPGA
- 用于FPGA的LCD显示，已验证是好使的。包括两个程序，VHDL编程。-LCD display for FPGA, is so that the verified. Includes two programs, VHDL programming.
uart
- 本设计用接口芯片的VHDL的设计方法，通过对MAX232串行通总线接口的设计，掌握发送与接收电路的基本设计思路，并进行串口通信-This design using VHDL design methodology interface chip, through the MAX232 serial communication bus interface design, master the basic design ideas to send and receive circuits, and se
FPGADM9000AVerilog
- FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
FPGAADS8364
- FPGA控制AD采样芯片ADS8364，电力行业应用很广-FPGA control AD chip ADS8364 sampling
ARMaFPGA
- ARM与FPGA结合的几十篇文章，非常有参考价值，工程师必备-ARM and FPGA combination of dozens of articles
cnt60
- 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.