资源列表
fenpin
- FPGA的一个分频程序，FPGA时钟频率问100MHz，进行100000000分频。-A sub-frequency program FPGA, FPGA clock frequency asked 100MHz, for 100 million frequency.
LIP1201CORE_dll
- Verilog DLL sOURCE CODE
Dac
- 这是一款用VHDL语言编写的对外部DA芯片的控制程序，所用DA转换芯片是TI公司的TLC5615.-This is a VHDL languages used on the external DA chip control procedures, using DA converter chip is TI
tlk1221jiaoyan_k
- 采用8B/10B编码方式，以不同的模式插入K28.5码进行数据校验，验证tlk1221芯片的数据传输是否正确，观察收发数据是否一致。-To check the data which is transceived by the way of 8B/10B coder/decoder by asserting K28.5 code in different mode and to observe that whether these data have been missed in the tran
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
edastudy
- 介绍EDA技术历史和现状及发展趋势，设计方法，其中包括一个小的例程-Describes the history and current status of EDA technologies and development trends, design methodology, which includes a small routine
pingpangchengxu
- 基于vhdl的实验仿真源码，包含完整的各项文件，是一个乒乓球游戏的小实验。-Linux embedded system based on the simulation source code, including the integrity of the document is a table tennis game is a small experiment.
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
1213
- 是十六位乘加器的VHDL语言描述。是我的课程设计。很好用。成绩是优秀-Is a sixteen by adder VHDL language descr iption. My course design. Good use. Performance is excellent
4位乘法累加器
- 4位乘法累加器，有需要的下吧，其他位的可以自行修改~-Multiplication accumulator 4
SRAM_Write_read
- SRAM读写的VHDL实验,通过对写入的数据与读出的数据进行比较,判断读写SRAM是否成功-SRAM read and write VHDL experiments on written data and read data to compare, to judge the success of SRAM read and write
R61526-initial-code
- initial code to set up the R61526 LCD controler