资源列表
div_1p5
- 时钟1.5分频的Verilog代码，简明扼要！-Clock frequency of 1.5 Verilog code, clear and concise!
SOPC
- 这是基于DE2平台的sopc实验,对初学者很具有参考价值-This is based on the DE2 platform sopc experiment is a reference value for beginners
sdram_mdl
- FPGA控制SDRAM程序，包括初始化、读写-SDRAM Initial and Read Write
QuartusII_Handbook
- 适合atera开发者参考学习的Quartus II 中文版操作手册-Quartus II Handbook
ALU
- ALU logic using Verilog
sdram_test
- FPGA测试程序，使用XC3S250E对SDRAM进行读写的测试程序，SDRAM使用的是HY57V281620， 大小为128M。-FPGA test procedure, the use of XC3S250E SDRAM read and write on the test procedure, SDRAM using HY57V281620, size of 128M.
470P2F07
- sqrt root using verilog
state-machine
- 状态机，独热码实验，简单的Verilog语言设计For NJU，简单易行-State machine, one-hot code experiment, a simple Verilog language design For NJU, simple
crc16
- crc16 module for SDIO DAT line calculation
synplify_ref_ug
- Synplify指导手册，内有vhdl、verilog、system verilog等综合详细指导，非常好的进阶资料喔！虽是英文的，但来自官方，绝对可靠喔！-Synplify guide, there vhdl, verilog, system verilog detailed, comprehensive guide, very good advanced data Oh! Although in English, but from the official, absolutely relia
sdram_ex9
- 深入浅出玩转FPGA代码 实验9sdram模块 基于EP1C3-Layman Fun FPGA code module based on experimental 9sdram EP1C3
LEDtest
- VHDL语言实现流水灯，通过按键控制显示方向，流水快慢-VHDL language flow lights show through the key control direction, flow speed