资源列表
mux4_to_1
- 四选一选择器的Verilog HDL编程，在Quartus II中实现了四选一数据选择器的功能。-Four elected a selector Verilog HDL programming, in the Quartus II in the four election data selector function
DE2_NET
- 基于altera公司EP2C35672C6的DE2板子的光盘中的自带文件。DE2_NET，网络模块。-Based on the DE2 board altera company EP2C35672C6 CD in its own file. DE2_NET, network modules.
tlc5628VHDL
- VHDL实现对TLC5628 AD芯片的时序控制,vhdl对时序的控制不仅高速,而且控制时序清晰,容易实现-vhdl counter tlc5628
cpu
- 给定指令系统的处理器设计,指令字长16位，包含10种操作-Given instruction processor design, 16-bit instruction word length, contains 10 kinds of operations
vhdltestbench
- testbench,VHDL的，适合初学者使用-testbench
rs232
- 基于QuartusII的RS232的串口编程实验，包括有波特率的改变-Based on the RS232 serial port programming QuartusII experiments, including the baud rate change
ad706_7276
- DA7276 的verilog 代码，时序还算精准，可直接复制使用-DA7276 of the verilog code, timing still accurate, can be directly copied using
I2CController
- Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx
DS1820
- DS18B20温度传感器，用verilog语言实现-DS18B20 temperature sensor, with the verilog language
washmachine
- 用VHDL语言描述了一个洗衣机的全部功能。包括洗涤，漂洗，脱水三种功能。洗涤完成后有蜂鸣音，并有数码管显示倒计时。-With the VHDL language to describe all the features of a washing machine. Including washing, rinsing, dehydration three functions. Beep after the completion of washing, and a digital display c
AHDL
- AHDL教程 硬件描述语言,Altera 的硬件描述语言AHDL,AHDL电路设计举例-Hardware descr iption language AHDL, Altera hardware descr iption language AHDL, AHDL circuit design example
mms
- （1）三位数的电子密码锁，通过输入的数字控制密码锁的开关 （2）开锁期间用户可自行设置密码 （3）输入密码正确开锁 -(1) The three-digit electronic code lock, through the input of the digital control lock switch (2) unlock their own during the user to set a password (3), enter the unlock password is c