资源列表
coef_reload91
- Altera 的系数可重载的滤波器代码，来自其官方网站-Altera filter coefficients can be overloaded code, from its official website
fenpinq
- VHDL分频器的设计，可以产生奇数和偶数次分频-VHDL Divider
LCD12864xianshihanzi
- 12864显示汉字，很好的，在CPLD实验板上通过验证-12864 display Chinese characters, very good, validated in the CPLD experiment board
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
16FFT
- 基于FPGA的16点FFT实现VEILOG-FPGA 16FFT VERILOG
SPI_Wishbone_Controller
- FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware descr iption language to achieve
ads7883
- FPGA实现对ADS7883的控制以及数据采集串行转并行-FPGA implementation of the ADS7883' s control and serial to parallel data acquisition
test_ad9852
- 使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。-Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.
floatadd
- 浮点数加法器的源代码,实现浮点数的加法功能，浮点数遵循的是IEEE745标准-floating_piont addition
opencore
- 基于FPGA的视觉采集系统的实现，verilog源码-FPGA-based visual collection system, verilog source
statemachine
- 用VHDL实现的有限状态机，还有modelsim仿真文件，及仿真结果-VHDL implementation using finite state machine, there modelsim simulation file, and the simulation results
rs_encorder
- RS编码的fpga实现，详细的vhdl文档，可以硬件实现。-RS coding fpga implementation, detailed documentation of vhdl can be implemented by hardware.