资源列表
microblaze-elf-tools-20060213.tar
- FPGA 上的嵌入式系统设计实例，SPARTEN-3E-FPGA, embedded system design example, SPARTEN-3E
tPad_Picture_Viewer
- tPad DE2-115/70可用的图片浏览设计程序，原装程序，可下载到带触摸板的DE2开发板上调试，代码可修改-tPad DE2-115/70 picture browsing design program available, the original program, with a touch pad can be downloaded to the DE2 board debugging, code can be modified
count_plus_last
- 对电机的编码器输入的正交编码信号进行4倍频处理 ，生成一个新的计数脉冲 ，同时判断电机的转动方向，输出一个方向标志电平信号，从而可以让DSP知道电机的转速和方向。-On the motor encoder inputs of the quadrature encoder signals 4 octave treatment, generates a new pulse count and at the same time to determine the direction of motor r
DDS-STC89C52-DAC0800-FPGA.doc
- 电子设计大赛，波形发生器，基于单片机和FPGA的DDS信号源。-Electronic Design Contest, waveform generator, microcontroller and FPGA-based DDS signal source.
Nios_II_Software_User_guide_chinese
- Nios II 设计中文版学习资料，适合初学者学习-The Chinese version of Nios II design of learning materials, suitable for beginners to learn
DVI_Demo_C3H_PortB
- DVI_Demo_C3H_portB HSMC-DVI card
1602LCD-Verilog
- 用FPGA控制在LCD1602上显示一段字符串。可以对LCD1602的控制有更深的了解-Using FPGA to control the LCD1602 display a string. LCD1602 can have a better understanding of the control
vhdl
- 基于vhdl的数字时钟；24制，带有定时，闹钟等功能。-VHDL-based digital clock 24 system, with time, alarm clock functions.
60seconds
- 60秒秒表设计，可暂停和分段计数等，所有功能是利用verilog HDL来描述，最后下载到CPLD/FPGA才能运行。-60 seconds stopwatch design, may be suspended and the sub-count
sdram_control.RAR
- 基于XILINX FPGA的SDRAM 控制器代码。VERILOG HDL代码编写-SDRAM CONTROLER
DE2_70_AUDIO
- altera ed2 -70开发板关于音频处理的原始代码1-altera ed2-70 Development Board on the audio processing of the original code 1
DE2_i2sound
- DE2开发板的音频控制程序，对WM8731的控制通过I2C总线来实现的，该代码是音频解/编码器配置的参考程序。-DE2 board audio control program the WM8731 control through the I2C bus, the code is the reference program audio solution/encoder configuration.