资源列表
sdh1
- 本段代码是关于SDH帧的操作的一段VHDL的代码。 主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame he
lcd1602
- 1602液晶显示控制 verilog程序 -1602 LCD Control verilog
VHDL
- 7段数码管译码器和8421码十进制计数器的程序-7 segment digital tube, and 8421 yards decimal decoder program counter
ps_2_keyboard
- 用VHDL语言编写的ps2键盘程序，可以在de2实验板上运行。初学者适用-VHDL language with the ps2 keyboard program, you can experiment in the de2 board to run. For beginners
DE2_CCD_detect
- DC2的用户手册，包括硬件原理图，软件编程程序，班子器件使用方法等-DC2 owner s manual, including the hardware schematics, software programming procedures, the use of devices such as team
I2C
- 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
juanjima
- 卷积码的生成程序,为(2,1,3)移位寄存器的卷积码生成-Convolutional code generation process for the (2,1,3) convolutional code of the shift register to generate
test
- PIC18F452的1602LCD显示程序，经过本人验证-Display program the PIC18F452 1602LCD
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
rs232
- fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
verilog
- Verilog桶形移位寄存器，实现不溢出移位-Verilog barrel shift register, the shift towards non-overflow
97B
- 这是电子设计大赛的97年b题简易数字频率计的fpga一种做法。-This is Electronic Design Competition 1997 b problem simple digital frequency meter fpga practice.