资源列表
VHDLLPM
- 应用vhdl语言，调用lmp块，非常有用，电子类设计必备-Application vhdl language, called lmp block, very useful, necessary electronic design
CVBS
- CVBS，用于生成模拟视频信号，NTSC/PAL可选-CVBS Signal Generator，NTSC/PAL could be selected
beep
- verilog写的控制喇叭的FPGA程序。-written in Verilog FPGA speaker control procedures.
quartusii10.1_handbook
- altera公司退出的最新quartusii10.0的手册，使用说明。-The latest company to exit quartusii10.0 altera manuals, instructions for use.
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
shuzizhong
- Verilog写成的数字钟 可以在ISE或者quartus环境下运行仿真-Verilog digital clock can be written in the ISE environment or running simulation quartus
sine
- Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
key_xiaodou
- 该资料是用vhdl编写的按键消抖程序，按键消抖在使用按键的数字电路中非常重要，如果不对按键信号进行处理，有可能会出现大量错误的按键信号。文件key_xd.vhd是按键消抖程序，文件key_xd.vwf是仿真波形文件。该程序已经通过仿真测试，并且在电路板上调试通过，效果理想。-The information is written in the key consumer vhdl shaking procedures, key consumer shaking in digital circuits
verilog
- 用Verilog语言描述比较器,数据选择器-Verilog language used to describe comparators, data selector
dpram
- FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
DE2_70
- DE2-70 入门实验，非常不错的入门指导书-DE2-70 Introduction to experimental, very good introductory guide book
counter_3
- 三种计数器的verilog实现,二进制计数器,格雷码计数器,约翰逊计数器.初学硬件描述语言可参考。-Three kinds of counter verilog implementation of a binary counter, gray code counter, Johnson counter beginner hardware descr iption language can refer to