资源列表
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
mydesign
- FPGA实现简易数字频率计设计。自己设计，绝对原创-FPGA realization of simple digital frequency meter design. Their own design, an absolute original
wannianli
- 采用VHDL语言编写的万年历程序，可在液晶上显示！-Using VHDL language calendar procedures, can be displayed on the LCD!
zigbee_sensor
- ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear qua
2C20
- 红色飓风的编程资料 培训的资料开发板上的-usb
Coding
- 这是用VHDL语言编写的4位比较器，用了三种描述进行编写-This is the VHDL language with the 4-bit comparator, used to prepare three kinds of descr iptions
APB
- It s the verilog source code for AMBA APB 2.0 Slave
GFverilog-hdl
- 伽罗华域的乘法器的设计，使用有限域设计乘法器-Galois field multiplier design, the use of finite field multiplier design
liftbd53
- 小波提升算法5_3 verilog 源码-Wavelet lifting algorithm 5_3 verilog source
QEP_FOR_ENCODER
- ALTERA MAX Ⅱ EPM570上QEP的源码，已经通过测试。-ALTERA MAX Ⅱ EPM570 source code on the QEP has been tested.
cpu2
- 另一个简单的16位VHDL的CPU程序~~~包含简单的加减乘除移位等操作，适用于课程设计-Another simple VHDL' s CPU 16-bit program ~ ~ ~ contains simple calculation shift and other operations for course design
quartus
- 基于vhdl语言描述的16*32点阵静态显示程序，分为单板显示和多板显示。-Static vhdl language to describe 16* 32 dot matrix display program, divided into veneer display and multi-panel display.