资源列表
AlteraFPGA
- FPGA原理图，可以用作最小FPGA系统的制作-FPGA schematics, can be used for the production of the smallest FPGA system
5B6B
- FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or b
Nios_II_timer
- 本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusI
TRDB_DC2
- DE1/DE2CCD摄像头Verilog源代码。-DE1/DE2CCD camera Verilog source code.
mul
- 八位乘法器的VHDL程序，按照乘法的运算规则利用分支语句判断所有情况，最后累加求的结果-8 multiplier VHDL programs, in accordance with rules of multiplication operations to determine all the circumstances of the use of a branch statement, the final cumulative result of demand
50M
- verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
traffic-light
- 基于VHDL语言开发实现交通灯的功能,实现倒计时，直行，向左转向右走的功能控制-traffic light design
calculator
- VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL
lcd_test
- Xilinx Spartan-3E实验板上基于verilog控制lcd屏幕A到Z反复轮转显示。-Xilinx Spartan-3E verilog based test control board lcd screen A to Z repeated rotary display.
SPI_MISO
- SPI-MOSI程序,奇主机输出，从机输入-SPI
median-filter
- 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation