资源列表
ug_ram
- RAM design for FPGA in verilog
fsm
- VHDL新手入门：有限状态机练习（三段式结构）-VHDL Getting Started: Finite state machine exercises (three-stage structure)
SystemverilogSource
- systemverilog程序，需要的朋友可以参看-SystemVerilog procedures need friends can see
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
FIR
- FIR结构数字滤波器，64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
FPGA-basedmultipliersCSDcode
- 基于FPGA的CSD编码乘法器（在MATLAB环境中）-FPGA-based multipliers CSD code (in MATLAB environment)
1
- 用VHDL实现地铁售票系统-Use VHDL to achieve subway ticketing system
lcd12864_avalon_interface
- 12864液晶的ip核，niosII，avalon总线。-12864 LCD ip nuclear, niosII, avalon bus.
count
- 用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the
gh_timer_8254
- VHDL Source code for 8254 timer/counter
gh_vhdl_lib
- VHDL Library for 8254 timer/counter core