资源列表
Spartan3ADSP_MB_Example_10_1
- ISE 嵌入式开发实例，主要支持Sparten3E-ISE Embedded Development instance, the main support Sparten3E
communicate-with-the-computer
- 用Altera Quartus II 的VHDL语言完成的串口与电脑通讯的源代码-The use of Altera Quartus II VHDL language to complete the serial port to communicate with the computer source code
ModelSim_Altera_61d_Exercises
- 很好的学习文档，对于软件的理解很有用。好好看，-Good learning document is useful for the understanding of the software. Good to see,
verilog_code
- verilog的大量实例，可以供初学者使用-a large number of instances of verilog
two_d_dct_serial
- Verilog codes for 2D Discrete Cosine Transform (DCT)
uartvhdl
- VHDL语言实现的UART IP核，比较实用-VHDL language to achieve the UART IP core, more practical
mem32_to_pcitarget_verilog
- This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
FPPG_CPLD_VHDL
- Polish documentation of FPGA, CPLD and VERILOG. Many examples and datasheets.
calc
- 用FPGA设计的简易计算器,包括按键模块,数码管模块-Use the FPGA design simple calculator, including key module, digital tube module
fpga_16bit
- Use FPGA to light on LCD module
ddc
- 数字下变频，vhdl代码，包含CIC和HF滤波-vhdl