资源列表
add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
FixToFloat.将16位二进制有符号纯小数转换为32位单精度浮点数
- 将16位二进制有符号纯小数转换为32位单精度浮点数。实际应用时，最好加tsu、tco约束条件，速度会快些。,There will be 16-bit binary decimal symbol is converted to pure 32-bit single precision floating point. Practical applications, it is best to increase tsu, tco constraints, the speed will be faste
用 vhdl 设计含异步清零和同步时钟使能
- 用 vhdl 设计含异步清零和同步时钟使能的十进制加法计数器。再用 vhdl 设计含异步清零和同步时钟使能的十进制加减可控计数器。 -With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter
voting 表决VHDL程序设计
- 7人表决VHDL程序设计，，表决的原则是输入“1”代表同意，“0”代表不同意，当同意的人数大等于4人时电路输出为“1”，否则为“0”。 ①用VHDL语言写出完整的程序。 -7 voting VHDL programming
同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序
- vhdl实现spi可以同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序，fpga cpld-vhdl spi can achieve devices with a SPI interface to communicate with devices on the SPI interface to read and write vhdl source code control
system 完成远程通信的整体任务
- Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件-Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and op
sdram_vhdl_lattice.rar
- lattice sdram 控制器VHDL源代码,Sound code of Lattice Sdram Controller based on VHDL
基于fpga的多功能电子钟的设计
- 基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊,FPGA-based multi-functional electronic clock design to use would like to help everyone ah
SPIBusVerilog.rar
- SPI串行总线接口的Verilog实现，详细讲解实现过程。,SPI serial bus interface Verilog realization elaborate on the realization of the process.
RSdecoder.rar
- cpld/fpga RS(204,188)译码器的verilog程序,cpld/fpga RS (204,188) decoder of the Verilog program
6tapFIR.rar
- 6阶FIR+verliog+分布式算法（DA）,6 bands FIR+ Verliog+ Distributed Arithmetic (DA)
Serial.rar
- 基于MAX2运用Quartus实现串口通信,MAX2-based use of Quartus Serial Communication