资源列表
digital_lock
- 数字密码锁verilog源代码，包括键盘输入，控制模块，和显示模块。-Digital code lock verilog
RAW2RGB
- 图像由RAW向RGB格式转换的verilog源代码实现-Images from the RAW format to RGB conversion Verilog source code implementation
test
- 数字中频正交解调的matlab仿真程序，简单带通信号的正交解调实现-Digital IF quadrature demodulation matlab simulation program, a simple bandpass signal quadrature demodulator to achieve
DPLL_TEST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
STFT
- 短时傅里叶变换的FPGA实现零重复度使用了fft的IP核设计-When the Fourier transform of the FPGA to achieve zero repeatability using fft IP core design
rgb2ycrcb
- 基于fpga的RGB转YcRcB源程序，verilog语言-Fpga-based RGB to YcRcB source, verilog language
data_scramble
- 用verilog 语言编译数字通信中的符号扰码，预防长1或长0的出现-a great complied code of data sramble for OFDM
CP_adder
- 用verilog 语言实现数字通信中最先进的技术之一中的OFDM技术中的添加循环前缀，可以减少码间干扰，并实现符号同步-a great complied code of cyclic prefix for OFDM which is good for intersymbol interference and inter channel interference
bt656_decode
- bt656 标准的解码 verilog 语言-bt656 decode
gwnseq
- verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）-verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence
ad7606_control
- ad7606 fpga接口 程序 ，实现ad7606的串口 读写，数据缓存-ad7606 controller,writen by verilog.
hpi
- 实现FPGA控制DSP的HPI接口，使用verilog接口-Achieve FPGA DSP HPI interface control, use verilog interface