资源列表
用 vhdl 设计含异步清零和同步时钟使能
- 用 vhdl 设计含异步清零和同步时钟使能的十进制加法计数器。再用 vhdl 设计含异步清零和同步时钟使能的十进制加减可控计数器。 -With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter
A/D转换芯片TLC2543的verilog编程
- A/D转换芯片TLC2543的verilog编程，根据TLC5243的datasheet编写，程序简单，结构清晰，可以借鉴应用-A/D converter chip TLC2543 the verilog programming
TLC2543
- 使用Verilog实现的AD采样，很有用的！-Implemented using Verilog AD sampling, very useful!
fsk
- FSK 完整 支持两板间 通信 位同步 帧同步-FSK full support for communication between the two plates synchronization frame synchronization
TFTLCD
- 基于FPGA的彩屏LCD控制器，800*480，显示彩条，TFT LCD型号AT070TN83-The TFT Lcd controller based on FPGA.The Matrix is 800*480,it can display color bands.
speed control
- calculate pulse signal's duty cycle, and control output signal's duty cycle which can be used to motor control(calculate pulse signal's duty cycle, which can be used to motor control)
Matlab的FIR数字滤波器的设计与仿真
- Matlab的FIR数字滤波器的设计与仿真(Design and Simulation of FIR digital filter for Matlab)
E7_1_LMSSim
- lms算法蒙特卡诺仿真，可以自行修改步长因子以及滤波器的阶数，查看仿真结果(Mont Kano simulation of LMS algorithm.You can modify the step factor and filter order by yourself, and see the simulation results.)
AIC23
- IIc总线控制AIC23，启动信号，停止信号等，以及AIC23初始化。(IIc bus controls AIC23, start signal, stop signal, and AIC23 initialization.)
RS422通信代码
- 28335通信程序，RS422程序代码，源代码(28335 communication program, RS422 program code)
AD7606_SPI
- 基于DSP28335 SPI的AD7606数据采集(Data Acquisition of AD7606 Based on DSP28335 SPI)
dsp
- 实现DTMF信号的输出和检测功能。。。。。。。。。。。。。。。。。。(Implementation of DTMF Signal Output and Detection Function)