资源列表
ad5399
- AD5399是一款串行输入、双通道、12位数模转换器，可采用二进制补码数字编码。。 用Verilog实现其配置与功能-AD5399 is a serial input, dual-channel, 12-bit DAC, digital code can be twos complement. . Configuration and use Verilog functions to achieve its
8-bit_Alu
- This is a simple 8bit ALU that is coded in VHDL
Phase_Meter
- 无正负的带显示的周期信号相位差测量实现的程序代码-Unsigned band show the periodic signal code phase measurement achieve
verilog_pingpang
- verilog 语言的写的乒乓操作，通过两个寄存器实现。-verilog language, written in ping-pang operation, achieved through two registers.
ctc16
- 一个定时器/计数器，里面实现了两个定时计数器，每个都可以写入方式控制器，以实现定时或者计时功能！-A timer/counter, which implements two timer counters, each of which can be written mode controller to achieve the function of time or the time!
noise
- 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
dif_jiaorao
- FPGA适用的加扰和差分编码程序，VHDL描述，适用于Xilinx FPGA-for Xilinx FPGA
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
iir_par
- IIR parallel VHDL FPGA
pci9054
- PCI读写控制程序 PCI9054与SRAM连接-PCI9054 PCI read and write control procedures connected with the SRAM
FIFOMXN
- 该VHDL描述的是一个简单的先进先出存储器-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
S-35390A-IIC
- 用GPIO口模拟IIC接口，可以发送和接收多个字符，参照S-35390A RTC芯片命令格式编写。-use the GPIO pin to simulate the IIC interface, based on the S-35390A RTC clock chipset command format, can send or receive single/multi byte command/data.