资源列表
is61lv25616
- 以is61lv25616为例，用verilog实现的SRAM-SRAM implemented verilog
Four-ways-of-contest
- 基于vhdl硬件设计语言而设计的四路抢答器-Based on VHDL designed hardware design language road 4 contest device
Addr_Generator
- 其中start是开始信号，上升沿启动控制单元；CLK是工作时钟；CtrlAddr是读取控制字时的地址；CtrlData是读取的控制字；Reading是读信号；EOP是本次AD采样完成信号，只有当AD1和AD2均完成后EOP才为高；EN是允许信号，启动分频器、地址发生器；N是分频系数；Addr1和Addr2分别是AD1和AD2数据存储的起始地址；NUM1和NUM2分别是采样点数。 控制字分别表示分频系数为2，AD1起始地址为1，采样点数5，AD2起始地址为3，采样点数为4。 -Where
FPGA-drive-12864
- FPGA驱动12864液晶,一般可以显示我们想显示的，只要相应的适当修改。-The FPGA drive, can generally 12864 LCD display we want to show, as long as the corresponding appropriate modification.
Dac714
- dac714的控制程序，包括spi数据通信，转换控制-dac714 control procedures, including the spi data communications, switching control
encoder
- 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
FT245
- 在FPGA实现一个与外围USB FIFO 通信的FIFO控制核-The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
PWM-control-LED--
- PWM控制LED灯亮度程序 提供的代码仅供参考 在使用时需要自己一定的修改添加-PWM control of LED brightness provides the code for reference in the use of certain modifications need to add their own
VHDL-language
- 用VHDL语言完成4位锁存器、测频控制器的设计-VHDL language to complete 4-bit latch, the measured frequency controller design
BCH-dec
- 基于C的BCH纠错码研究，已经做了调试，和你好用。-C-based study of the BCH error correction code, debugging has been done, and Hello to use.
test5
- 用VHDL设计8位算术逻辑运算器，并将运算结果显示通过俩个七段数码管显示-Design with VHDL 8-bit arithmetic and logic devices, and computing results show that by two seven-segment LED display
configue_dac
- AD5624模拟数字转换芯片SDI接口配置代码-AD5624 analog-digital converter chip SDI interface configuration code