资源列表
YINYUEBOFANGQI
- 本程序是一个基于VHDL的音乐播放器学习资料，适合初学者学习-YINYUE BO FANG QI
lcd_disp
- lcd字符显示，已经在Spartan3e板子上验证通过了，初学者可以下来-lcd character display, has been verified by Spartan3e on board, and beginners can take a look down
led_water
- 非常适合初学者学习,FPGA的开发程序，大家可以参考参考-It is very important
HW3_P1
- Clock Controller There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CL
ALUALUcontrol
- 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
Move071221133_32
- 用Verilog HDL语言或VHDL语言来编写，实现32位的桶形移位器。 并在Quartus Ⅱ上实现模拟仿真；-With the Verilog HDL language or VHDL language to write to achieve 32-bit barrel shifter. To achieve in the Quartus Ⅱ simulation
VHDL
- 分频跑马灯数码管示范代码能实现分频跑马灯数码管示范-Crossover Marquee digital control Model Code
IU3
- sun公司的sparc结构之整数处理器vhdl源码-The file is the RTL of the Sparc s integer unit.
VERILOG
- 一本很好的Verilog课件，通俗易懂简单明了适合初学者，给大家分享了~-A very good Verilog courseware, simple easy to understand for beginners, for everyone to share ~
RS_decoder
- Reed solomon decoder based on table-lookup method VHDL code
wtut_edif
- Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock