资源列表
miaobiao
- VHDL语言实现的秒表设计，具有分秒，计数清零等功能-VHDL language implementation of the stopwatch design, with the minutes and seconds, counting functions such as Clear
calculator
- 此源码为在xilinx环境中用VHDL实现计算器，实例可用xcs40xl-4-pq208戓xc2s100-6pq208FPGA来实现-The source code in xilinx environment using VHDL implementation calculators, examples can be xcs40xl-4-pq208 Ge xc2s100-6pq208FPGA to achieve
bist
- design for test Test and Design-for-Test for memory bist-design for test
Ringcounter
- ringcounter verilog HDL example code
ALU_mo
- ALU architecture for a microcontroller by using VHDL synthesis
P_to_ser
- parallel to serial data converter using VHDL
debounce
- a key debounce logic using VHDL
7segment
- a seven segment display using VHDL
primeno
- how to detect a prime number using VHDL
8051IP
- 用硬件描述语言写的8051IP CORE-Using hardware descr iption languages written 8051IP CORE
MIPS_IP
- 用硬件描述语言写的MISP IP CORE-Using hardware descr iption languages written in MISP IP CORE
8086IP
- 用硬件描述语言编写的8086 IP CORE-Using hardware descr iption language of the 8086 IP CORE