资源列表
serial
- 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
state_mm
- 有限状态机源码，verilog语言编写。非常详细的示范了FSM状态机的编写。-Finite state machine source code, verilog language. A very detailed model of the FSM state machine preparation.
cpu_4
- 用verlog语言写的4指令CPU的实现，运行于MAX+plusII10.2环境下-Written in four languages with verlog instruction CPU implementation, running on the MAX+ plusII10.2 environment
Signal2
- VHDL语言写的序列信号发生器，放心使用，没问题-VHDL code
ALU2
- VHDL 做的ALU ，我们的实验代码,已经验证，可以使用-VHDL do ALU, our experimental code, has been verified, you can use
experiment1
- VHDL实现寄存器的代码，最后一个是完全正确的，前几个有些问题。-VHDL implementation register code, the last one is completely correct, the first few there are some problems.
JPEG2000
- 用于JPEG2000的53小波VHDL源码-53 for the JPEG2000 wavelet VHDL source code
EDAshiyanbaogao
- 关于VHDL的关于数字跑表的eda的课程设计！-failed to translate
songer
- VHDL语言实现设计音乐功能模块的源代码，-VHDL language implementation design of musical function module source code,
yyy
- 能检测11100101的序列，时钟信号控制输入的序列。-11,100,101 sequence can detect the clock signal control input sequences.
music_1
- 能通过eda实验箱上按键开关实现发出do，re，me等七个中低高音。-Experimental boxes through eda button switches to achieve given do, re, me and other 7 in the low treble.
verilog_instance
- 20多个十分实用的verilog例子，如状态机，除法器等-More than 20 very practical verilog examples, such as state machines, divider, etc.