资源列表
seven_lcd
- 七段数码管显示的时钟程序VHDL代码 ISE编译环境-SEVEN seg VHDL ISE CLOCK
verilog_code
- 《Verilog HDL程序设计教程》程序源码(王金明)-" Verilog HDL Programming Tutorial" program source code (Wang Jinming)
vhdltest
- 自己设计的几个VHDL程序，包括译码器电路，多路开关，比较器应用，和16乘8RAM电路，各模块及最终的顶层原理图和引脚我都已给好，希望对大家的学习有所帮助-A few of their own design VHDL procedures, including the decoder circuit, multiple switches, comparator applications, and 16 by 8RAM circuit, each module and final top-leve
Audio_Bit_Counter
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Audio_In_Deserializer
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Audio_Out_Serializer
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
cmd_pro
- 用于SD卡通信控制部分的命令收发部分，verilog语言描述-Communications control part for the SD card send and receive part of the command, verilog language to describe the
Avalon_Audio
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Clock_Edge
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
SYNC_FIFO
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
data_pro
- 用于SD卡通信控制部分的数据收发部分，verilog语言描述-SD cards for some of the data send and receive communication control part, verilog language to describe the
yunlei
- 实现出租车计费系统，包含所有的源文件-Taxi billing system to achieve