资源列表
ADC_Ctrl
- 用verilog编写FPGA与AKM394A之间的接口程序-Verilog between FPGA and Ak5394A interface code
ad_converter
- 基于spi接口的数模转换控制（FPGA verilog源码）-Spi interface-based digital-analog conversion control (FPGA Verilog source code)
altera_sdram
- 基于quartus平台的sdram控制器设计（verilog 源码）-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
VGA
- 简单的通过FPGA控制实现的VGA显示（verilog源码）-Through the FPGA to control the realization of the VGA display (Verilog source code)
lcd1602
- proteus仿真，基于51单片机的系统仿真，很好的 很实用的 ，可以尝试-Proteus
ber_tester_m
- 基于FPGA的误码测试仪 （已注释） --锁相环-M序列生成模块--数据接口模块- --模拟信道模块---本地M序列生成模块--同步模块--误码统计模块--显示模块--FPGA-based BER tester
Digital-signal-processing-FPGA
- 本书详细讨论了FPGA在数字信号处理中的应用问题-This book comprehensively elaborated FPGA in digital signal processing application problems.
ml605_fmc_xm104_ibert_rdf0066_13.1_c
- ML605_Reference_Designs:ml605_fmc_xm104_ibert_rdf0066,xilinx开发板的fmc设计例程，包括源码和下载文件-ML605_Reference_Designs：fmc codes and download files include ace and bit file
ml605_PCIe_Gen1_x8_rdf0008_13.1_c
- ML605_Reference_Designs:ml605_PCIe_Gen2_x4_rdf0009,xilinx开发板的PCIe设计例程，包括源码和下载文件.verilog-ML605_Reference_Designs：PCIe codes and download files include ace and bit file
td
- 实现逻辑分析仪的通道选择。具体选择是有一个按键输入8位的控制信号与没路信号进行逻辑与当控制信号K(i)是‘1’是选择i路信号输出数据，当‘0’时输出全部为零不显示i路波形。-Realize the logical analyzer of chanSpecific choice is to have a keystroke eight control signals and no way signal logic and when the control signal K (I) is 1 i
dianziqin-music-bofangEDA
- EDA编程 电子琴乐曲播放 EDA程序VHDL语言-Keyboard music playing eda program
Ctw8816--palcV
- TW8816关于CVBS视频格式到到TFTLCD的有关内部寄存器的配置表 -CVBS video format on the TW8816 to TFTLLCD register the relevant internal table