资源列表
CORDIC_testt
- cordic旋转以及testbench，可以作为givens旋转的一个单元使用，有很强的工程价值-cordic and testbench
ep1c12_23_motor
- FPGA控制电机程序，以及在12864上显示当前的速度等，并且具有速度分档功能-The FPGA control motor program, and display the current speed on the 12864, and with speed sub-file function
phase
- 2012年江苏省电子设计竞赛，测相位差程序。可分辨相位的超前于滞后，经测试稳定可靠！-Electronic Design Contest in 2012, Jiangsu Province, the phase difference measurement procedures. Distinguished phase ahead of the lag has been tested and is stable and reliable!
ov_control
- ov7620CMOS控制的verilog代码，用vsync.href,pclk共同控制摄像头同步。在signaltap以验证-The verilog code ov7620CMOS control jointly control the camera using vsync.href, pclk synchronization. In signaltap to verify
uart_232
- RS232的verilog控制程序，8位数据传输，奇校验，一个停止位，已经过singnaltap验证-RS232 verilog control procedures, the eight data transmission, odd parity, one stop bit, verification has been singnaltap
chuot
- code VHDL/ Verilog for Mouser using FPGA: Xilinx, Altera
SharpSharpSharpodd_divide_frequency
- 该语言的功能是实现奇数分频，以7分频为例~希望对需要者有用~-The language function is odd division, divided to hope useful for those who need to
RS21
- 该源代码是RS（31，19）码的编码程序，采用的是VerilogHDL语言，这是个完整的程序，能够直接在ISE软件上运行-The source code is RS (31,19) code coding procedures, the is VerilogHDL language, which is a complete program can be run directly in the ISE software
RS2
- 该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间-The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this
CDMA-REsult-wave-form
- CDMA result waveform
manchester_verilog
- 曼彻斯特码生成器（Verilog源代码）,可以在FPGA上进行验证。-Manchester code generator (Verilog source code), and can be verified on a FPGA.
pc_cfr_v3_0_msim
- xilinx pc-cfr仿真代码,供参考-xilinx pc cfr matlab code ,for reference