资源列表
viterbi-ip-core-using-mothed
- FPGA的Viterbi译码器IP 核的使用说明，简单方便，一目了然。还能进行tcm译码，功能强大呀-Instructions for use of the FPGA Viterbi decoder IP core, easy glance. Can tcm decoding powerful!
UART_TX
- xilinx urat发送端口源码程序，可直接调用的模块-The xilinx urat to send port source programs, the module can be called directly
verilog_
- VERILOG语言应用，基本语法结构，应用实例介绍-VERILOG language applications, basic grammatical structures, application examples introduced
ISE9.1
- ISE软件中文教程，介绍了程序的编写，综合，仿真，上传。-ISE software Chinese tutorial, program preparation, synthesis, simulation, and upload.
dds_ds558
- DDS数据手册，介绍了其应用原理，各个引脚的使用说明。-DDS Data Sheet describes the application of the principle, the use of descr iption of each pin.
simple_count.tar
- Simple program to count and make an output blink
fudian_sub
- 实现32位浮点减法器，具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
fudian_mul
- 实现32位浮点减法器，具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
aa
- 本程序是用Xilinx ISE 软件编写的。它完成了（7,3）码的编码工作。里面有源程序和用于仿真的测试文件-The program is written using the Xilinx ISE software. (7,3) code encoding. Inside source for simulation test file
yima
- 本程序是在Xilinx ISE上编写的，它完成了（7,3）码的译码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed the decoding of the (7,3) code. Source and for the simulation of the test file inside
juanji1
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的编码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed the (2,1,6) convolutional code encoding. Source and for the simulation of the test file inside
juanji2
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的译码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed (2,1,6) convolutional code decoding. Source and for the simulation of the test file inside