资源列表
YUV_to_RGB
- YUV to RGB converter in verilog
IQIT
- Inverse quantization and DCT for h.264 in verilog
cnt60
- vhdl数字钟，有校时校分整点报时的基本功能-vhdl digital clock school, the school divided the whole point timekeeping function
VHDL
- 电路主要由七个模块组成：时钟产生模块用于产生1KHz的扫描时钟和1Hz的时钟；二分频模块用于对1Hz的时钟信号二分频；测量/校验选择模块用于功能选择；计数模块用于对输入的cp信号计数；送存选择、报警电路根据选择的量程送存信号并显示单位，在超出所选量程时报警；锁存器锁存要显示的结果；扫描显示模块在1KHz的扫描时钟下，依次扫描三个数码管，并显示结果。-The circuit consists of seven main modules: clock generation module is use
si_xi_fen
- Quartus环境下，用verilog ＨＤＬ写的光电码盘的四细分程序，用于获得转向和转速-Quartus environment, use verilog HDL write light code disc four segmentation procedure, are used to obtain steering and speed
ad976
- FPGA实现AD976的自动采样的Verilog HDL程序，所采用的是AD976的模式一，已调试成功-AD976 FPGA to realize the automatic sampling of the verilog HDL program, the is AD976 model a, already debugging success
ad976_CS
- FPGA实现AD976的自动采样的Verilog HDL程序，所采用的是AD976的模式二，即采用CS信号，已调试成功-AD976 FPGA to realize the automatic sampling of the Verilog HDL program, the AD976 is the mode 2, i.e., to use the CS signal, already debugging success
1602
- VHDL实现的1602液晶显示程序，已调试成功-VHDL realization of 1602 liquid crystal display program, already debugging success
RS232
- VHDL实现的RS232通信程序，发送和接收都已实现-VHDL realization of RS232 communication procedures, send and receive are realized
Prentice---Verilog.HDL_A.Guide.to.Digital.Design.
- Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented i
SHA_1_V
- 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL implementation
SHA-256
- 基于FIPS 180-4标准的SHA-256算法的verilog HDL实现-SHA-256 algorithm based on FIPS 180-4 standard verilog HDL implementation