资源列表
LSY_wave
- 比赛时写的李萨如波形发生器的代码，用verilog写的，里面集成数据采集和DDS波形发生。-Game when writing the the Lissajous waveform generator code, written in verilog the inside integrated data acquisition and DDS waveform generation.
16_MUX
- AM2901 Benchmark - test patterns for output shifter-AM2901 Benchmark- test patterns for output shifter
display
- display_stim.vhdl Testbench for display Benchmark
scan2
- 数码管扫描显示，两位数码管显示，当扫描频率高时就是静态显示。-Digital the tube scan display, two digital tube display is a static display, high scanning frequency.
my_half_add
- 基于FPGA的半加器源码，声明，有verilog编写的-FPGA-based half adder source, statement, written in verilog
codigo-fuente-rxbot
- rxbot latest version
ddr_verilog
- DDR控制器的VERILOG代码；状态机；读写；刷新等操作-ddr controller,verilog
extension_pack_latest.tar
- This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code. Automatic count stop/start value generation functions. You enter a time duration and clock frequency and the v
mean-simulation
- 一个均值仿真的代码！真的很好！完整的工程文件-A mean simulation code! Really good! Complete project file
add_led
- 利用K1,K2来代替A2 A1 的数据输入。 利用K3,K4来代替B2 B1 的数据输入。 我把A0和B0都设置成1了。 所以一开始数码管显示的是E.应为111加111就等于E 数码管显示相加结果-K1, K2 to replace A2 A1 data input. K3, K4 to replace B2 B1 data input. A0 and B0 are set to 1. So beginning digital display E. should be 111 p
jiafaqi
- 利用FPGA，VHDL设计一个加法器控制LED。-The use of FPGA, VHDL design an adder control LED.
FPGA_DS18B20
- 利用FPGA，vhdl语言设计，控制DS18B20芯片温度检测。-FPGA, vhdl language design, control DS18B20 chip temperature detection